1. Field of Invention
This invention relates generally to semiconductor memories and specifically to a page buffer having a negative level shift circuit.
2. Description of Related Art
Typically, nonvolatile semiconductor memories such as, for instance, EEPROM and Flash EEPROM, employ a plurality of NMOS floating gate transistors as memory cells. However, recent advances in the semiconductor industry have led to the development of a PMOS non-volatile memory cell. Examples of PMOS memory cells and the advantages thereof are described in commonly owned U.S. Pat. Nos. 5,666,307 and 5,687,118, and in co-pending U.S. Pat. No. 5,706,227 entitled "Triple Poly PMOS Flash Memory Cell" and filed on Dec. 7, 1995, and Ser. No. 08/568,544 entitled Double Poly Split Gate PMOS Flash Memory Cell" and filed Dec. 7, 1995, which is U.S. Pat. No. 5,706,227 all incorporated herein by reference.
A PMOS memory cell of the type disclosed in U.S. Pat. No. 5,687,118 is shown in FIG. 1. The cell 10 is formed in an n- well region 12 of a p- substrate 14. A p+ source 16 and a p+ drain 18 are formed in the n- well region 12. A channel region 20 extends within the n- well 12 between the p+ source 16 and the p+ drain 18. A polysilicon floating gate 22 is insulated from the n- well region 12 by a thin oxide layer 24. A control gate 26 is insulated from the floating gate 22 by an insulating layer 28. In its intrinsic or erased state, the cell 10 has a negative threshold voltage (V.sub.T).
The cell 10 is programmed by inducing the accumulation of charge, i.e., electrons, on the floating gate 22. The cell 10 may be programmed using a variety of mechanisms, including channel hot electron (CHE) injection, Fowler-Nordheim (FN) Tunneling, band-to-band tunneling (BTBT) induced electron injection, and various combinations thereof. When programmed, the cell 10 has a positive V.sub.T. It is the difference between the program V.sub.T and the erase V.sub.T of a cell 10 which determines the "binary state" thereof. For instance, a programmed cell 10 represents the binary value "1", and an erased cell 10 represents the binary value binary "0". To read the binary state of a cell 10, a read voltage which lies between the program V.sub.T and the erase V.sub.T is applied to the control gate 26 of the cell 10. Thus, during a read operation the cell 10 conducts a channel current if in a programmed state, i.e., if its V.sub.T is positive.
The cells 10 may be included within a variety of array architectures such as, for instance, those described in the commonly owned U.S. Pat. No. 5,801,994 entitled "Nonvolatile Memory Array Architecture" and filed Aug. 15, 1997, Ser. No. 08/948,531 entitled "PMOS Memory Array Having OR Gate Architecture" and filed Oct. 9, 1997, and Ser. No. 08/947,850 entitled "Nonvolatile PMOS Two Transistor Memory Cell and Array" and filed Oct. 9, 1997, all incorporated herein by reference. In such array architectures, the control gates 26 of cells 10 in a common row are connected to an associated word line, and the p+ drains 18 of cells 10 in a common column are connected to an associated bit line. In some of these array architectures, the cells 10 are formed in a common n-well region which, in turn, is electrically coupled to the p+ sources of the cells 10.
Proper operation of PMOS memory cells such as the cell 10 shown in FIG. 1 requires bias voltages different from those in operation of NMOS memory cells. As a result, the peripheral circuitry (e.g., page buffers, charge pumps, row decoders, and so on) typically employed in an NMOS non-volatile memory are not suitable for use in a PMOS non-volatile memory. Rather, optimum performance of a PMOS nonvolatile memory requires unique peripheral circuitry. For instance, to facilitate programming of the cell 10 using BTBT induced electron injection, approximately 3 volts is applied to the N-well 12 and the p+ source 16, approximately 8.5 volts is applied to the control gate 26 via the selected word line, and approximately -5.5 volts is applied to the p+ drain 18 via the selected bit line.
NMOS memory cells, on the other hand, typically do not require negative voltages during programming. Thus, page buffers typically employed in an NMOS non-volatile memory are not designed to handle negative voltages and, as a result, are not suitable for use with negative voltages. For instance, application of such negative voltages to page buffers typically employed with NMOS memory cells may result in the transistor breakdown. Thus, a page buffer suitable for handling negative voltages during program operations of a PMOS memory cell is, therefore, desirable.